The application relates to a semiconductor integrated device (or semiconductor device), and can be applied to, for example, a semiconductor integrated device for display drive.
JP-A-2009-194119 or U.S. Pat. No. 8,421,250 corresponding thereto relates to a semiconductor chip for an LCD (Liquid Crystal Display) driver. The above documents disclose a technique in which an alignment mark is formed in an alignment mark forming region by a metal wiring layer flush with a pad layer, and dummy patterns are respectively arranged in a wiring layer, a device layer, and an element isolation layer which are located below the region.